1. Field of the Invention
The present invention relates generally to packaging substrates having an electrical connection structure and methods for fabricating the same, and more particularly to, a packaging substrate having an electrical connection structure for electrically connecting a chip and a method for fabricating the same.
2. Description of Related Art
The current flip chip technique involves electrically connecting a semiconductor chip to a packaging substrate, wherein the semiconductor chip has a plurality of electrode pads on an active surface thereof, and the packaging substrate has a plurality of conductive pads corresponding to the electrode pad. A solder structure or other conductive adhesive material is disposed between the electrode pads and the corresponding conductive pads for providing electrical connection and mechanical connection between the semiconductor chip and the packaging substrate.
Referring to FIGS. 1A to 1F, a conventional method for fabricating an electrical connection structure for a packaging substrate is shown. First, as shown in FIG. 1A, a substrate body 10 with a plurality of conductive pads 11 on at least one surface thereof is provided. Then, as shown in FIG. 1B, a solder mask layer 12 is formed on the surface of the substrate body 10 and a plurality of openings 120 are formed in the solder mask layer 12 to expose the conductive pads 11. Subsequently, as shown in FIG. 1C, a mold plate 13 is disposed on the solder mask layer 12 and the mold plate 13 has a plurality of openings 130 corresponding to the openings 120 of the solder mask layer 12. Thereafter, as shown in FIG. 1D, solder bumps 14 are formed in the openings 130 of the mold plate 13 by coating or printing. Then, as shown in FIG. 1E, the mold plate is removed. Finally, as shown in FIG. 1F, the solder bumps 14 are reflowed to form solder bumps 14′ to provide electrical connection for the substrate body 10.
In the above-described method, since the solder bumps 14 are filled in the openings 120 of he solder mask layer 12 and the openings 130 of the mold plate 13 by coating or printing, the quality of the solder bumps 14 is not easy to control, which can easily lead to poor uniformity in thickness and size of the solder bumps 14, thereby adversely affecting the electrical connection quality.
Further, in a flip-chip bonding packaging process, when the line width and pitch of a packaging substrate are reduced, the joint strength is decreased as the joint size is reduced. When temperature in a thermal recycling process of the fabrication process varies or the completed package is in use, the joint strength is not sufficient to endure the stress caused by a CTE difference between the chip and the substrate, thus 15 resulting in joint separation or breakage between the solder bumps 14′ and the electrode pads and failing to provide a preferred electrical connection.
Therefore, how to overcome the above-described drawbacks has become urgent.